1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a highly integrated semiconductor device exhibiting improved leakage current characteristics and reliability without using a separate lightly doped drain (LDD) structure and a method for fabricating such a highly integrated semiconductor device.
2. Description of the Prior Art
The recent trend to produce highly integrated semiconductor devices results in a reduced channel length of a single transistor in order to increase the performance and integration of semiconductor devices using the transistor.
However, where a transistor has a reduced channel length, the intensity of electric field at the drain of the transistor increases, so that a semiconductor device using the transistor exhibits a degradation in its off-state characteristic and reliability.
A number of research efforts have been made to solve the above-mentioned problems. The commonly used method is to form spacer oxide films on side walls of a gate electrode formed on a semiconductor substrate, thereby forming an LDD region for providing a gradual concentration distribution of impurity ions in a channel direction in the semiconductor substrate in order to achieve a reduction in the intensity of electric field.
Now, this method, which forms a transistor having an LDD structure, will be described in conjunction with FIGS. 1 and 2.
In accordance with the conventional method, a gate oxide film 2 is first formed over a semiconductor substrate 1, as shown in FIG. 1. A gate electrode 3 is then formed on the gate oxide film 2.
Using the gate electrode 3 as a mask, impurity ions having a conductivity different from that of the semiconductor substrate 1 are implanted in a low concentration in the semiconductor substrate 1. The resulting structure is annealed to form an LDD region 4 in the semiconductor substrate 1.
An oxide film (not shown) is then deposited over the entire exposed surface of the resulting structure, as shown in FIG. 2. The oxide film is anisotropically etched, thereby forming spacer oxide films 5 on the side walls of the gate electrode 3, respectively.
Thereafter, impurity ions having a conductivity different from the semiconductor substrate 1 is implanted in a high concentration in the semiconductor substrate 1. The resulting structure is then annealed, thereby forming source/drain regions 6.
However, the above-mentioned method has various problems.
For example, in the conventional method, it is required to respectively optimize the ON and OFF characteristics of the semiconductor device because a degradation in the ON-state characteristic is exhibited in proportion to a reduction in the intensity of electric field obtained by the LDD region.
To this end, it is essentially required to optimize the dose of the low concentration impurity ions and the width of the spacers.
In particular, the width of the spacers should be more precisely adjusted because it exhibits considerable influence on a variation in the characteristics of the semiconductor device when the semiconductor device has a reduced channel length. However, it is difficult to obtain a desired process margin due to limited process conditions such as a limited thickness of the spacer oxide film, a limited thickness of the gate electrode, a fine adjustment required in the anisotropic etching to form spacers and damage of the spacer oxide film caused by plasma.